Complementary metal oxide semiconductor (CMOS) integration requires two gate materials, one having a work function near the valence band edge of the semiconductor material in the channel and the other having a work function near the conduction band edge of the same semiconductor material. In CMOS devices having a silicon channel, a conductive material having a work function of about 4.0 eV is necessary for n-type metal oxide semiconductor field effect transistors (NMOSFETs) and another conductive material having a work function of about 5.0 eV is necessary for p-type metal oxide semiconductor field effect transistors (PMOSFETs).
In conventional CMOS devices employing polysilicon gate materials, a heavily p-doped polysilicon gate and a heavily n-doped polysilicon gate are employed to address the needs. In CMOS devices employing high-k gate dielectric materials, suitable materials satisfying the work function requirements are needed. So far, identification of materials for a dual work function metal gate electrode system has presented some challenges. In particular, a high-k material metal gate stack for p-type field effect transistors that is capable of withstanding a high temperature thermal cycling encountered during a conventional semiconductor processing sequence has proven to be illusive so far.
Due to the difficulties encountered in providing suitable materials for a pair of dual work function metal gate electrode system, hybrid implementation of a high-k metal gate and a conventional polysilicon gate has been known in the art, in which a high-k material metal gate is employed for one type of transistors, i.e., n-type field effect transistors, and a conventional polysilicon gate is employed for another type of transistors, i.e., p-type field effect transistors. However, integration of the two types of gate electrodes introduces difficulties since the two types of gates have different requirements for spacer structures. On one hand, a low-k dielectric spacer or an oxide spacer is desirable on a polysilicon gate electrode to reduce parasitic capacitance between the polysilicon gate electrode and the source and drain regions. On the other hand, a high-k material metal gate requires protection of the high-k material from subsequent oxidation since an unstable oxygen content in the high-k gate dielectric degrades or introduces uncertainty in the dielectric constant of the high-k material.
In view of the above, there exists a need for a semiconductor structure providing a high-k material metal gate and a semiconductor gate electrode, while providing stability of the composition of the high-k material as well as a low parasitic capacitance for the semiconductor gate electrode, and methods of manufacturing the same.